This invention relates to a method of bonding metals and to a technique for fabricating a semiconductor integrated circuit device using the method, which technique is effective when applied to a semiconductor integrated circuit device based on, for instance, the flip-chip system or TAB (Tape Automated Bonding) system.
In gate arrays or logic LSIs for microcomputers, etc., the number of terminals (input/output pins) for connection to external circuits has recently been rapidly increasing due to the increases in the number of functions and the packaging density of integrated circuits. The wire bonding system, in which connection of a semiconductor chip to external circuits is effected through wires bonded to bonding pads provided at the peripheral portions of the chip, has therefore been reaching the limit of application thereof. Besides, the wire bonding system has drawbacks in that the need for the wiring in an internal circuit region to be laid around to the bonding pads in the peripheral regions leads to a larger wiring length, resulting in a delay in signal transmission rate. The wire bonding system is thus unsuitable for mounting a logic LSI which requires high-speed operations.
For the reasons as mentioned above, attention has been paid to the flip chip system in which a semiconductor chip is mounted on a substrate through CCB bumps (projected electrodes) provided on Al electrodes of the chip by use of a solder material, and to the TAB system in which bumps comprising an Au-Sn eutectic alloy are provided on the Al electrodes and the semiconductor chip is mounted through the bumps onto leads provided on a principal surface of an insulation film. Especially, the flip chip system is an extremely effective mounting system for an increase in the number of pins of the semiconductor chip because the system makes it possible to provide terminals not only in the peripheral areas of the semiconductor chip but on the entire surface of the chip, namely, also in the internal circuit region of the chip. With the terminals provided in the internal circuit region, moreover, the wiring length is reduced, which makes the flip chip system extremely effective for use as a system for mounting a high-speed LSI.
As a method of providing the CCB bumps in the above-mentioned flip chip system, there have been used a solder vapor deposition method and a solder ball supply method. In the solder vapor deposition method, for instance, the CCB bumps are provided as follows. First, thin films comprising Cr, Cu and Au, for instance, are sequentially vapor deposited on the Al electrodes of the semiconductor chip to provide a soldering primary coat (BLM: Bump Limiting Metallization). Of the primary coat for soldering, Cr in the lowermost layer is provided for preventing an allying reation between the solder bump and the Al electrode, whereas Cu in the intermediate layer is provided for enhancing the wettability by solder, and Au in the uppermost layer is provided for preventing corrosion of Cu therebeneath. Next, a solder film comprising a pb-Sn alloy or the like is selectively vapor deposited on the soldering primary coat, and the solder film is melted by heating in a melting furnace filed with an inert gas atmosphere, to form spherical CCB bumps by utilizing the surface tension of the solder film thus melted. On the other hand, the solder ball supply method is a method in which contaminants such as oxides, moisture, oils and fats, etc., deposited on the surfaces of the Al electrodes are removed completely by ion impacts and then spherical solder balls are superposed on the cleaned surfaces in an ultra high vacuum, followed by bonding, as for instance described on pages 88-91 of "Yosetsu Gijutsu (Welding Technology)" issued in July, 1987.
A chip carrier is one of the semiconductor integrated circuit devices based on the above-mentioned flip chip system. The chip carrier is described in, for instance, Japanese Patent Application Laid-Open (KOKAI) Nos. 62-249429 (1987) and 63-310139 (1988).
FIG. 15 shows a sectional structure of a chip carrier described in the above-mentioned literature. The chip carrier 50 has a packaged structure in which a semiconductor chip 54 connected through CCB bumps 53 to electrodes 52 provided on a principal surface of a package substrate 51 comprising a ceramic material, such as mullite, is hermetically sealed (or encapsulated) by a cap 55. The cap 55 comprises, for instance, aluminum nitride (AlN) and is bonded to the principal surface of the package substrate 51 through a sealing solder 56.
The back side (upper surface) of the semiconductor chip 54 is bonded to a lower surface of the cap 55 through a heat-transmitting solder 57, in order that the heat generated from the chip 54 is transmitted through the solder 57 to the cap 55. Electrodes 52 on the lower surface of the package substrate 51 are provided thereon with CCB bumps 58 for mounting the chip carrier 50 on a module substrate or the like. The CCB bumps 58 are bonded to the electrodes 52 by, for instance, the solder ball supply method, after fabrication of the chip carrier 50 is completed. The package substrate 51 is provided therein with an internal wiring 59 comprising W (tungsten), for instance, through which the electrodes 52, 52 on the principal surface and the lower surface of the package substrate 51 are electrically connected.
To fabricate the above-mentioned chip carrier, first, the CCB bumps of the semiconductor chip are positioned accurately on the electrodes on the principal surface of the package substrate by a chip mounting device. In this case, a flux is applied to bonding portions of the CCB bumps and the electrodes. The flux is applied for removal of natural oxide films formed on the surfaces of the solder constituting the CCB bumps and for preventing the re-oxidation of the solder surfaces at the time of reflow. A further purpose of flux application is to enhance the wettability by solder at the time of reflow.
Subsequently, the package substrate is transferred into a reflow furnace. It is necessary, in this transfer, to prevent the slippage of the CCB bumps due to vibration or the like. The flux serves also for the prevention of the slippage. The reflow furnace is provided therein with an inert gas atmosphere, in which the CCB bumps are re melted by heating, whereby the semiconductor chip is bonded, with its face side down, to the principal surface of the package substrate (namely, facedown bonding is effected).
Next, the cap is soldered to the principal surface of the package substrate by the sealing solder. In addition, the back side of the semiconductor chip is soldered to the lower surface of the cap by the heat-transmitting solder. The soldering of the cap to the principal surface of the package substrate is carried out by preliminarily depositing a sealing preliminary solder on the principal surface of the package substrate and base portions of the cap, applying a flux to the surfaces of the preliminary solder, then placing the cap on the principal surface of the package substrate, and re-melting the preliminary solder by heating in the reflow furnace. The soldering of the back side of the semiconductor chip to the lower surface of the cap is carried out by preliminarily depositing a heat-transmitting preliminary solder on the lower surface of the cap or on the back side of the semiconductor chip, applying a flux to the surface of the preliminary solder, and then re melting the preliminary solder by heating in the reflow furnace.
The operation of soldering the cap to the principal surface of the package substrate and the operation of soldering the back side of the semiconductor chip to the lower surface of the cap are carried out in the same step. The sealing solder and the heat-transmitting solder, therefore, comprise solder materials having approximately equal melting temperatures. Besides, the melting temperatures of the sealing solder and the heat-transmitting solder are lower than the melting point of the solder constituting the CCB bumps; otherwise, the CCB bumps would be re-melted at the time of re meting the preliminary solders by heating in the reflow furnace, and the CCB bumps would collapse under the load of the cap, leading to short circuit between adjacent ones of the CCB bumps. For this reason, the CCB bumps comprise a high-melting solder, for instance, a Pb Sn alloy with an Sn content of about 2 to 3% by weight (melting temperature=about 320.degree. to 330.degree.C.), whereas the sealing solder and the heat-transmitting solder each comprise a low-melting solder, or instance, a Pb Sn alloy with an Sn content of about 10% by weight (melting temperature=about 290.degree. to 300.degree. C.).
Thus, in the chip carrier fabrication step, which involves the step of mounting the semiconductor chip on the principal surface of the package substrate through the CCB bumps and the step of soldering the cap to the principal surface of the package substrate to encapsulate (or hermetically seal) the semiconductor chip or of soldering the back side of the semiconductor chip to the lower surface of the cap, the acceptability of the soldering affects greatly the reliability of connection of the CCB bumps, the reliability of hermetic seal (or encapsulation) of the package and the cooling efficiency.
Another method of bonding the solder balls is known, in which contaminants such as oxides, moisture, oils and fats, etc., deposited on the bonding surfaces are completely removed by ion impacts, and the materials are superposed one on the other and bonded in an ultra-high vacuum, as described on pages 88-91 of the "Yosetsu Gijutsu (Welding Technology)" issued in July, 1987.